250 MSPS acquisition board(型番:ALPHA250)

仕様(一部を抜粋)

Programmable logic, processor and memory
System On Chip Zynq 7020 XC7Z020-2CLG400I
Memory 512 MB of DDR3L SDRAM
Processor ARM dual-core CPU
100 MHz low-noise RF front-ends
RF ADC 2 channels, 14-bit, 250 Msps, DC coupled
RF DAC 2 channels, 16-bit, 250 Msps, DC coupled
Input to output latency 90 ns
Input / Output 1 Vpp, 50 Ω